Scan chains are used to obtain access to internal nodes of an integrated circuit and simplifying testing of ICs by setting and observing the sequential elements (e.g., flip-flops) thereof. Scan chains include flip-flops that together operate as a shift register when a scan enable signal is asserted. A single input pin may be used to provide test data to the scan chain and a single output pin can be connected to the output of the scan chain to read the state of each flip-flop in the scan chain. Typically, the test data are test patterns that are shifted in via the scan chains using a functional clock signal. The results are then shifted out to output pins of the IC and compared to expected results to determine possible failures.
Scan chains are typically connected to functional logic of the IC. During functional mode, data toggling causes scan chain nets dedicated to tests to toggle and consume power. Additionally, since the scan chain nets are typically connected to functional nets outside of sequential elements, the scan chains can also hinder functional performance.
A typical solution to address the performance issue is to have a dedicated scan output port on a sequential element which will unload the functional output of the cell. To address the power issue, a NAND gate can be added to the scan data output path to gate the signal when not in scan mode. The addition of a NAND gate to gate off the scan output from the sequential element, however, increases the area overhead. The additional NAND gate can also increase leakage power at all times and increase dynamic power during scan shift operations.